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Full text of "Hitachi Hitachi Dot Matrix Liquid Crystal Display OCR"

HITACHI MICROCOMPUTER SYSTEM 



DOT MATRIX LIQUID CRYSTAL DISPLAY 
CONTROLLER & DRIVER 
LCD- I (HD44780) 
USER'S MANUAL 

—PRELIMINARY— 




Q 



quan-.u 



QGroniCft 



iiOX 

Bramley. 



HITACHI MICROCOMPUTER SYSTEM 

DOT MATRIX LIQUID CRYSTAL DISPLAY 
CONTROLLER & DRIVER 
LCD- 1 (HD44780) 
USER'S MANUAL 

—PRELIMINARY— 



HITACHI 40-i-n 



MARCH, 1981 



40-1-11 



When using this manual, the reader should keep the 
following in mind: 

1. This manual may, wholly or partially, be subject to 
changes without notice. 

2. All rights reserved: No one is permitted to re- 
produce or duplicate, in any form, the whole or 

a part of this manual without Hitachi's permission. 

3. Hitachi will not be responsible for any damage to 
the user that may result from accidents or any other 
reasons during operation of his unit according to 
this manual . 

4. This manual neither ensures the enforcement of any 
industrial properties or other rights, nor sanctions 
the enforcement right thereof. 



Information contained in this publication is believed to be accurate and 
reliable. However, responsibility is assumed neither for its use nor for 
any infringement of patents of rights of others that may result from its 
use. No license is granted by implication or otherwise under any patent 
or patent right of HITACHI or others. 

HITACHI reserves the right to change specifications for this product in 
any manner without notice. 



MARCH, 1981 



. PREFACE 

The LCD-n (HD44780) is a dot matrix liquid crystal display controller* 
driver LSI that displays alphanumerics , kana charactors and symbols. 

It drives dot matrix liquid crystal display under 4-bit or 8-bit 
microcomputer control. 

All functions needed for dot matrix liquid crystal display drive are 
internally provided on one chip. 

The user can complete dot matrix liquid crystal display systems with 
less number of chips by using the LCD-H (HD44780) . 



CONTENTS 

Outline 1 

Features 2 

Logical Structure and Function 3 

3.1 Symbol Diagram 3 

3.2 Pin Assignment and Dimentional Outline 4 

3.3 Terminal Function 5 

3.4 Block Diagram 6 

3.5 Function of Each Block 7 

3.6 Interfacing to HPU 16 

3.7 Reset Function 17 

Instruction 18 

4.1 Outline 18 

4.2 Description of Details 20 

Electrical Characteristics 23 

5.1 Absolute Maximum Ratings 23 

5.2 Electrical Characteristics 24 

5.3 Timing Characteristics 27 

How to Use HD44780 29 

6.1 Interface to 8-bit MPU 29 

6.2 Interface to Liquid Crystal Display 31 

6.3 Power Supply for Liquid Crystal Display Drive 33 

6.4 Liquid Crystal Display Drive Waveform 36 

6.5 Connection with Driver LSI HD44100 38 

6.6 Correspondence Example of Instructions and Display 41 

Appendix 45 



. Outline 

The LCD-n (type No.HD44780 , hereinafter called HD44780) is a dot matrix liquid 
crystal display controller &driver LSI for display of alphanumerics, kana characters 
and symbols. It memorizes character codes (8 bits/character) sent from 
microcomputers or microprocessors (hereinafter called MPU)into display data RAM (DD RAM, 
80 bytes=640 bits, 80 character size), converts them to dot matrix character patterns 
of either 5*7 dots or 5*10 dots, which are then sent to the internal liquid crystal 
display driver. Since the HD44780 has an internal 16-common signal driver and 
AO-segment signal driver, one HD44780 can display up to 16 characters (in the case 
of 1 character being 5 X 7 dots, 1/16 duty). If a driver LSI HD44100 is externally- 
connected to the HD44780 , up to 80 characters can be displayed. 

The HD44780 is internally equipped with character generator ROM (CG ROM) that 
generates 160 types of alphanumerics, kana characters and symbols (character font 
5 X 7 dots, in conformity to JIS) and 32 types of special characters (Greek letters 
and others, character font 5 X 10 dots). Further, it is equipped with character 
generator RAM (CG RAM, 64 bytes=512 bits) in the size of 8 characters if with 
character font of 5 X 7 dots, or size of 4 characters if with 5 X 10 dots. CG RAM can 
be programmed for each application. The above feature offers a lot of convenience 
in actual use. The user can specify any character pattern for character generator 
ROM. For details, refer to "The LCD-H (HD44780) Breadboard User's Manual". 

To designate character display position, write an instruction into the 
instruction register from MPU via data bus and then write a character code into the 
data register via data bus. Since the HD44780 has a function of automatically 
shifting character display positions after character codes are written, character 
displays at continuous positions from the next operation on is possible, by writing 
only character codes. Also, since the HD44780 has the shift function of the entire 
display, display input from either left or right is possible. 

Since both of the display data RAM and character generator RAM can be read from 
MPU, whatever part that is not used for display can be used as general data RAM. 

The HD44780 is a CMOS LSI of 80-pin plastic flat package. It can transfer data 
in 4-bit-2-operation or 8-bit-l-operation, allowing interface to MPU of either 4 or 
8 bit. When combined with a CMOS MPU, the user can develop portable battery drive 
equipment utilizing low power consumption of the liquid crystal display. 



HITACHI 1 



2. Features 

.5x7 and 5^10 dot matrix liquid crystal display controller driver 
•Capable of interfacing to 4-bit or 8-bit MPU. 

•Display data RAM 80x8 bits (80 characters, max.) 

•Character generator ROM 

Alphanumerics and symbols: 96 types ;A-^Z, a-~z, etc. (5x7 dot character font) 

Kana characters and symbols: 64 types ; 7~-y , T J , etc.(5 x 7 dot character font) 

Special characters: 32 types;a, 6, ft, etc. (5x10 dot character font) 
•Character generator RAM 

Programmable: 8 types of 5 X 7 dot character font, or 
4 types of 5 X 10 dot character font 
•Both of display data and character generator RAMs can be read from MPU. 

•Internal liquid crystal display driver 16 common signal drivers 

40 segment signal drivers 
•Duty factor selection (selected by programs) 

1/8 duty: 1 line of 5x7 dots + cursor 

1/11 duty: 1 line of 5 X 10 dots + cursor 

1/16 duty: 2 lines of 5 X 7 dots + cursor 



•Maximum number of display characters 



No. of 

Display Lines 


Duty 
Factor 


Extentior 


ilD44780 


HD44100 


No. of Display Characters 


1-line 

display 


1/8 

1/11 

duty 


Not ., . 
provider. 


1 pc. 




8 charactersxl line 


Providea 


1 pc. 


9 pcs.(8 characters/pc.) 


80 charactersxl line 


2-line 

display 


1/16 
duty 


NOt -A A 

provided 


1 pc. 




8 charactersx2 lines 


Provided 


1 pc. 


4 pes. 

(8 characters^ lines/pc.) 


40 charactersx2 lines 



•Wide range of instruction function 

Display clear, Cursor home, Display ON /OFF, Cursor ON /OFF, 

Display character blink, Cursor shift, Display shift 
•Internal automatic reset circuit at power ON. 

•Internal oscillation circuit (with an external resistor or ceramic filter) 

- 

(External clock operation is possible.) 

•CMOS process 

•Logic power supply; A single+5V (excluding power for liquid crystal display drive) 
■Operation temperature range; -20 — H75°C 

(Device for -40~'+85°C is available upon request) 
•80-pin plastic flat package (FP-80) 



2 HITACHI 



3. Logical Structure and Function 
3.1 Symbol Diagram 



oat) 
3nt) 



Power Supply 

For Logic I 



Clock Terminals 



MPU Connecting 
Terminals 







COM, 


16 




V C c 
GND 
OSC, 
OSCj 


-COM, 6 


— / ■ 




SEG, 


♦ 




— S EG« o 


— f 




CL lf CL, 


* 




RS 


M, D 


— i 








R/W 








Vi 

v 2 






E 




-Vr 


DB — DB 3 






Vj 




-V- 


DB 4 ~-2B 7 






• v 4 

V s 

















Connected to 
Liquid Crystal 
Display Terminal 

Connected to 
] External Driver LSI 
HD44100 



Power Supply for 
Liquid Crystal 
Display Drive 



icters 



ie 
les 



les 



HITACHI 



3.2 Pin Assignment and Dimentional Outline 



(1) Pin Assignment 



SEG 



o"cTs~sf S S s £ 5 ssssszsss 

WWOOOOOOOOOOOOOOOOeococc 
wtoUOUUOUUUUOOCJUUUUQaQ 




UOOOOUUUOOOOOOOOUUUOOOQO 
W W CO W W W CO COCOCOCOCO COCOEOCO CO CO CO CO CO CO U O 



(2) Package Dimentional Outline (80 Pin Plastic Flat Package) 



2 5.2 ± 0.4 




1 5 




(FP-80) 



(Unit :mm) 



4 HITACHI 



3.3 Terminal Function 



Table 3 




ctional D 




Signal 
name 


No .of 
lines 


— 

Inpu t / 

Output 


ConriGC ted 
to 


Function 


RS 


1 


Input 


MPU 


Signal to select registers 

"n". Tncfriif fi on rppi'itpr ( frtr uri rpl 

Busy flag; address counter (for read) 
"1": Data register (for read and write) 


R/W 


1 


Input 


MPU 


Signal to select read (R) and write (W) 
: Write 
"1": Read 


£ 


I 


Input 


MPU 


Operation start signal for data read or write 


DB4 
DB7 


4 


Input/ 
Output 


Plr U 


T"i;it~a Vhiq nf Vi"ioHf>T nTflpT A 1 i npQ hai7i no hi Hi rprti nnal 

iJQtd U UD \J J- 111 gllC 1. KJ i UC i *-t llllco 11 a v 1 Ut U ± U X i t: L. 1 LUIl al 

tri-state. Used for data transfer between the MPU and 
the HD44780. DB7 can be used as a BUSY flag. 


DB W 
DBi 

J) 


4 


Input/ 
Output 


MPU 


Data bus of lower order 4 lines having bidirectional 
tri-state. Used for data transfer between the MPU and 
the HD44780. These four are not used during 4-bit 
operation . 




1 


Output 


HD44100 


Clock to latch serial data D sent to the driver LSI 
HD44100. 


CL 2 


1 


Output 


HD44100 


Clock to shift serial data D. 


M 


1 


Output 


HD44100 


Switch signal to convert liquid crystal drive waveform 
into AC. 


u 


1 


fin r I "1 ■ — 7 ' 

uucpuc 


ur*/i /■ i nn 
num luu 


Ch £1 T a c t" p T" n £1 1 - f" f» T"n Hsta f nrTPCnnn^i no 1~e~\ cmr-\\ /Tmunnn 

IjliaLdL LCI Jjd L Ltlll UdLd I — kJ L L coUUHUXllg UU C-d^Ll l^ULiullULi 

signal is serially sent in sequence. 
"0": Non selection 
"1": Selection 


COMi - 
COM 16 


16 


Output 


Liquid 

crystal 

display 


Common signal that are not used are made to non-selection 
waveforms. That is, COMg -COM^g are in non-selection 
waveform at 1/8 duty factor, and COM12 C0Ml6 are in 
non-selection waveform at 1/11 duty factor. 


SEGi^ 
SEGin 


40 


Output 


Liquid, 
crystal 
display 


Segment signal 


Vi ~V 5 


5 




.Power 
supply 


Power supply for liquid crystal display drive 


V CC ,GND 


2 






V cc ; +5V, GND; 0V 


osc 2 


2 






Terminals connected to resistor or ceramic filter for 
internal clock oscillation. 

In the case of external clock operation, the clock is 
input to OSCj. 



HITACHI 5 



i 

o 
I 



Vcc • 
GND • 
OSC, ■ 

osc,- 



RS 

R/W 

E 



DB 4 ~DD 7 



DB ~DB S ■ 



Power Supply 
for Liquid 
Crystal 
Display Drive 



V, ■ 
V,- 

V 
v 4 - 

kv,- 



H 


M 






H 


rt 








3 


IK 


cn 






X 


H> 


rt 






rt 


O) 


H 




a 


H 


rt 


c 


8 




c 


ft 


n 




o 


o 


ri 


rt 




o 






w- 




H 


H- 




c 




a 


O 


H 


3 




rt> 


3 


2 






l-t 















Address 
Counter(AC) 



Timing Generation 
Circuit 



H 


o 


r? 


K 


OQ 


ta 


r* 


at 




rt 




to 












a 




3 









Busy 
Flag 



7 •• 



Display Data 
RAM 
(DD RAM) 

80x8 bits 



Character 
Generator 

RAM 
(CG RAM) 

512 bits 

















rt- 


pa 


rt 


to 




OP 


CA 


M- 


3" 


n 


rt- 


r' 


Ml 


n 


rt 


H 





in 



Character 
Generator 

ROM 
(CG ROM) 

7200 bits 



M 



Parallel/Serial Data 
Conversion Circuit 
(Parallel Data-" Serial Data) 



o 

t) 3 
H 

rt 
< 
to 09 
« 3 
01 



EA 











en 




*- 






ft 




o 






00 


■ f 


1 






a 


0> 


cr 








rt 


H* 






3 





rt 


a 


rf 


















H' 


C/l 


r> 






< 


H- 


H- 






It 


0Q 


H 






rt 


3 


o 








B 


c 










ill 











40-bit Shift Register 



CL, 
C L, 
M 



16 

r»- 



COM, ~COM,« 



o 



oc 



rt 
rt> 

3 



CO 

o 



+0 



SEG, ~S EG 40 



.5 Function of Each Block 
(1) Register 

The HD44780 has two 8-bit registers, an Instruction Register (IR) and a Data 
Register (DR) . 

IR stores instruction codes such as display clear and cursor shift, and address 
information of display data RAM (DD RAM) and character generator RAM (CG RAM). 
IR can be written from MPU but not read by MPU. 

DR temporarily stores data to be written into the DD RAM or the CG RAM. Data 
written into DR from MPU is automatically sent to the DD RAM or the CG RAM as 
an internal operation. DR is also used for data storage when reading data from 
the DD RAM or the CG RAM. When address information is written into IR, data is 
• transferred to DR from the DD RAM or the CG RAM as an internal operation. Then, 
data transfer to the MPU is completed by the MPU reading DR. After the MPU 
reads DR, data of the DD RAM or the CG RAM at the next address is sent to DR 
for the next read from the MPU. 

Register selector (RS) signals select these two registers. 
Table 3.2 Register selection 



RS 


R/W 


Operation 








IR write as internal operations (Display clear, etc.) 





1 


Read of a BUSY flag (DB 7 ) and address counter (DBq ~-DBg) 


1 





DR write as internal operations (DR to DD or CG RAM) 


1 


1 


DR read as internal operations (DD or CG RAM to DR) 



(2) Busy flag (BF) 

When the Busy flag is "1", the HD44780 is in the internal operation mode, and 
the next instruction is not accepted at this time. As shown in Table 3.2, 
the Busy flag is output to DB7 when RS=0 and R/W=l. The next instruction must 
be written after checking that the Busy flag is "0". 

(3) Address counter (AC) 

The address counter (AC) assigns address to DD and CG RAMs. When as instruction 
for address is written in IR, the address information is sent from IR to AC. 
Selection of either DD or CG RAM is also determined concurrently by the 
instruction . 

After writing into (or reading from) DD or CG RAM display data, AC is 
automatically incremented by +1 (or decremented by -1) . AC contents are output 
to DBo- DB 6 when RS=0 and R/W=l, as shown in Table 3.2. 

(4) Display data RAM (DD RAM) 

The display data RAM (DD RAM) stores display data represented in 8-bit character 
codes. Its capacity is 80 x 8 bits, which can contain 80 characters . The display data 
RAM (DD RAM) that is not used for display can be used as general data RAM. 
Relation between DD RAM addresses and positions on the liquid crystal display 



HITACHI 7 



is as shown below. 

The DD RAM address (Add) which is set in the Address Counter (AC) is 
represented in hexadecimal. 

Upper Order Lower Order 



Bits 



Bits 



AC 



AC 8 



AC 5 



AC * 



AC 3 



AC 2 



AC 1 



AC 



Hexadecimal 
(Example) DD RAM address "4E" 



(digit) 
1-line 



1 








1 


1 


1 













\ 




A 




E 


/ 








v 4 

Display (N=0) 

1 2 S 


4 


5 










79 


80 





1 • 


2 


3 






4 E 


4 F « 


4 





Display 
Position 
DD RAM 
Address 



(a) When number of display characters is less than 80, the display starts from 
the head position. For example, 8 characters using 1 HD44780 are displayed 
as shown below: Display 



(digit) 


] 


2 


3 


4 


5 


6 


7 


8 —Position 




1-line 





1 


2 


3 


h 


5 


6 


7 


^DD RAM - fp£ 
Address 




When display shift 


operation 


is performed, the DD RAM address mi 


sves as 




1 


2 


3 


4 


5 


6 


7 


8 


(Left Shift 
Display) 





4 F 





1 


2 


3 


4 


5 


6 



















(Right Shift 
Display) 



(b) 16-character display using an HD44780 and an HD44100 is as shown below: 

1 2 3 4 5 6 7 8 B 10 11 12 13 14 15 16-- Display 



(digit) 
1-line 






1 


2 


3 


4 


5 


6 


7 


8 


9 


A 


B 


C 


D 


E 


F 



Position 
-DD RAM 
Address 



When display shift operation is performed, the DD RAM address moves as follows: 

(Left Shift 
Display) 



1 


2 


3 


4 


5 


6 


7 


8 


9 


A 


B 


C 


D 


E 


F 


1 




4 F 





1 


2 


3 


4 


5 


6 


7 


8 


9 


A 


B 


o c 


D 


E 



(Right Shift 
Dispaly) 



(c) Relation between display position and the DD RAM address when number of 

display digits is increased by using one HD44780 and two or more HD44100's 
can be considered extension of (b) . 

Since 8 digits can be increased for each additional HD44100 , display of up 
to 80 digits is possible by connecting 9 HD44100's externally. 



8 HITACHI 



•2-line Display (N=l) 

(digit. 



1- line 

2- line 






1 


2 


3 


4 




2 6 


2 7 < 




4 


4 1 


4 2 


4 3 


4 4 




6 6 


6 7 





Display 
39 40 «- „ ; / 
Position 

DI) RAM 
Address 



(a) When number of display characters is less than AO characters x 2 lines, 

2 lines starting from the head are displayed. Note that the first line end 

address and the second line start address are not consecutive. For example, 

when an HD44780 is used, 8 characters * 2 lines are displayed as follows: 

Display 
Position 



(digit) 
1-line 




2 


3 


4 


1 


6 


7 


8 





1 


2 


3 


4 


5 


6 


7 


2-line 


4 


4 1 


4 2 


4 3 


4 4 


4 5 


4 6 


4 7 



DD RAM 
Address 



When display shift is performed, the DD RAM address moves as follows: 

(Left Shift Display) 



1 


2 


3 


4 


5 


6 


7 


8 


4 1 


4 2 


4 3 


4 4 


4 5 


4 8 


4 7 


4 8 





2 7 





1 


2 


3 


4 


5 


6 




^ 7 


+.0 


4 1 


4 2 


4 3 


4 4 


4 5 


4 6 



(Right Shift Display) 



(b) 16 characters x 2 lines are displayed as follows when an HD44780 and an 
HD44100 are used: 



1 2 3 4 5 6 7 8 9 1 1 1 1 2 1 3 1 4 1 5 1 6 «~ 



1-line 





1 


2 


3 


4 


5 


6 


7 


8 


9 


A 


B 


o c 


D 


E 


F 


2-line 


4 


4 1 


4 2 


♦ 3 


4 4 


4 5 


4 6 


4 7 


4 8 


4 9 


4 A 


4 B 


4 C 


4 D 


4 E 


4 F 



Display 
Position 

- DD RAM 
Address 



H D 4 4 7 8 

Display 



A 



HD 4 4 1 

Display 



When display shift is performed, the DD RAM address moves as follows: 



1 


Z 


3 


4 


5 


6 


7 


8 


9 


A 


B 


C 


D 


E 


F 


1 


4 1 


4 2 


4 3 


4 4 


4 5 


4 6 


4 7 


4 8 


4 9 


4 A 


4 B 


4 C 


4 D 


4 E 


4 F 


5 






2 7 





1 


2 


3 


4 


5 


6 


7 


8 


9 


A 


B 


C 


D 


E 


6 7 


4 


4 1 


4 2 


4 3 


4 4 


4 5 


4 e 


4 7 


4 8 


4 9 


4 A 


4 B 


4 C 


4 D 


4 E 



(Left Shift 
Display) 



(Right Shift 
Display) 



HITACHI 9 



(c) Relation between display position and DD RAM address when number of 

display digits is increased by using one HD44780 and two or more HD44100's. 
can be considered extension of (b) . 

Since display columns are increased by 8 digitsx 2 lines for each 
additional HD44100, display of up to 40 digitsx 2 lines is possible by 
connecting 4 HD44780's externally. 

(5) Character Generator ROM (CG ROM) 

The character generator ROM generates character patterns of 5x7 dots or 5 X 10 
dots from 8-bit character codes. It can generates 160 types of 5><7 dot 
character patterns and 32 types of 5x10 dot character patterns. Table 3.3 
and 3.4 show correspondence between character codes and character patterns. 
Also, the user defined character patterns are available by mask-programming 
ROM. For details, refer to "The LCD-IE (HD44780) Breadboard User's Manual". 

(6) Character Generator RAM (CG RAM) 

The character generator RAM is the RAM with which the user can rewrite 
character patterns by program. In the case of 5 X 7 dots, 8 types of character 
patterns can be written and in the case of 5 X 10 dots 4 types. Write the 
character codes listed in the left edges of Table 3.3 and 3.4 to display 
character patterns stored in CG RAM. 

Table 3.5 shows relation between CG RAM addresses and data and display 

patterns . 

As shown in Table 3.5, area that is not used for display can be used as 
general data RAM. 



10 HITACHI 




Table 3.4 Correspondence between Character Codes and Character 



^\Higher 

Lowerx, 
4bit \^ 


oooo 


0010 


0011 


0100 


0101 


0110 


0111 


1010 


1011 


1100 


1101 


1110 


1111 


xxxxo'O 00 


CG 

RAM 

(11 







o 


p 


s 


P 






9 




a 


P 




xxxxOOO 1 


12) 


! 


1 


A 


Q 


a 


<1 


° 


T 


9 




a 


q 




xxxxoOlO 


(3) 


ii 


2 


B 


R 




r 


A 


•y 






e 




xxxxoni 1 


(4) 


# 


8 


C 


S 


c 


s 


j 




T 




£ 


oo 




XXXX01 00 


(5) 


$ 


4 


D 


T 


d 


1 




X 


\- 




u 


Q 




XXXXO 101 


!6> 


% 


5 


E 


U 


e 


u 




* 


t 


.3- 


a 


u 




xxxxO 110 


(7) 


& 


6 


F 


V 


f 


V 


j 


* 




3 


P 






xxxxo 111 


IS) 


9 


7 


G 


w 


■ 


w 


T 


* 




7 


J 


X 








xxxxl 000 


(1). 


C 


8 


H 


X 


h 


X 


■i 


9 




'J 




X 




xxxxl 001 


(2) 


) 


1 


I 


Y 


i 


y 


V 




/ 


;u 


— 1 


y 




ixxxxi 10 


(3) 


* 




J 


Z 


j 


z 








u 


j 


f 




xxxxioil 


(4) 


+ 




K 


c 


k 


{ 


* 


# 


t 


o 


X 






xxxxl 100 


(5) 


t 


< 


L 


¥ 


1 


1 


-t 




7 


9 


t 


m 




xxxxl 101 


(6) 






M 




m 


} 








~s 


£ 






xxxxl 1 10 


(7) 




> 


N 




n 


— > 


■ 


•fe 


* 


♦ 


n 






xxxxmi 


(8) 


/ 


T 







o 






y 






V 







12 HITACHI 



! 
I 

! 

! 



Table 3.5 Relation between CG RAM Addresses and Character Codes (DD RAM) 
and Character Patterns (CG RAM Data) 
(a) For 5x7 dot character patterns 



Character Codes- 
(DD RAM Data) 



765*8210 

♦-Higher Order Bits 
Lower Order Bits 



5 4 8 2 l c 
♦-Higher Order Bits 
Lower Order Bits-* 



CG RAM 
Address 




Character Patterns 
(CG RAM Data)' ' 



76543210 

♦-Higher Order Bits 
Lower Order Bits- 



Character 
Pattern 
Example (1) 

Cursor 
<— Position 



Character 
Pattern 
Example (2) 



Don ' t Care 



Note 1: Character code bits — 2 correspond to CG RAM address bits 3 ~5 
(3 bits:8 types).. 

2: CG RAM address bits 0—2 designate character pattern line position. 

The 8th line is the cursor position and display is performed in logical 
OR with cursor. 

3: Character pattern row positions correspond to CG RAM data bits 0~4, 
as shown in the figure (Bit 4 being at the left end). Since CG RAM 
data bits 5—7 are not used for display, they can be used as general 
data RAM. 

4: As shown in Table 3.3 and 3.4, CG RAM character patterns are selected 
when character code bits 4 — 7 are all "0". However, since character 
code bit 3 is an don't care bit, "R" display in the chatacter pattern 
example, for example, are selected by character code "00" (hexadecimal) 
or "08" (hexadecimal) . 

5: "1" for CG RAM data corresponds to selection for display and "0" for 
non-selection . 



HITACHI 13 



(b) For 5*10 dot character patterns 



Character Codes 
(DD RAM Data) 



7 8 5 4 3 2 1 

<-Higher Order Bits 
Lower Order Bits— 4 



5 4 8 2 10 

•-Higher Order Bits 
Lower Order Bits-» 



CG RAM 
Address 




Character Patterns 
(CG RAM Data) 



7 6 5 4 3 2 1 

♦■Higher Order Bits 
Lower Order Bits— » 



Character 

Pattern 

Example 



Cursor 
"Position 



Don't Care 



Note 1: Character code bits 1, 2 correspond to CG RAM address bits 4, 5 
(2 bits: 4 types) . 

2: CG RAM address bits 0~3 designate character pattern line position. 
The 11th line is the cursor position and display is performed in 
logical OR with cursor. 

Since the 12th ~ 16th lines are not used for display, they can be used 

as general data RAM. 
3: Character pattern row positions are the same as the positions for 

5x7 dot character patterns. 
4: CG RAM character patterns are selected when character code bits 4~7 

are all "0". However, since character code bit and 3 are don't care 

bits, "P" display in the character pattern example, for example, are 

selected by character code "00", "01", "08" and "09"(hexadecimal) . 
5: "1" for CG RAM data corresponds to selection for display and "0" for 

non-selection. 



14 HITACHI 



Timing Generation Circuit 

The timing generation circuit generates timing signals to operate internal 

circuits such as DD RAM, the CG ROM and the CG RAM. RAM read timings needed 

for display and internal operation timings by MPU accesses are separately 

generated so that they do not interfere with each other. Therefore, there 

will be no undesirable influence like flickering in areas other than display 

area of, for example, when writing data to the DD RAM. 

This circuit also generates timing signals to operate the externally 

connected driver LSI HD44100. 

Liquid Crystal Display Driver Circuit 

The liquid crystal display driver circuit consists of 16 common signal drivers 
and 40 segment signal drivers. When a character font and number of lines are 
selected by a program; the required common signal drivers automatically output 
drive waveforms, and other common signal drivers continue to output non- 
selection waveforms. 

The segment signal driver has essentially the same configuration as the driver 
LSI HD44100 (see Fig. 6.12). Character pattern data is serially sent through 
a 40-bit shift register and latched when all needed data has arrived. The 
latched data controls the driver to generate drive waveform outputs . 

The serial data is sent -to the HD443 00 externally connected in cascade and 

^ - - - -± J - ■ 

used for extension of number of display digits. 

Send of serial data starts always at the display data character pattern 
corresponding to the last address of the display data RAM (DD RAM) , and since 
serial data is latched when the display data character pattern corresponding 
to the starting address enters the internal shift register, the HD44780 
drives the head display and the rest displays corresponding to latter addresses 
are added with each additional HD44100. 



HITACHI 15 



3.6 Interfacing to MPU 

In the HD447N0, the data can be sent in either 4-bit 2-operation or 8-bit 1-operation so that 
it can interface to both 4 and 8 bit MPU's. 

(1) When interface data is 4 bits long, data is transferred using only 4 buses of 
DB4 ~ DB7 and DBo ~ DB3 are not used. Data transfer between the HD44780 and the 
MPU completes when 4-bit data is transferred twice. Data of the higher order 
4 bits (contents of DB4 ~ DB7 when interface data is 8 bits long) is transferred 
first and then lower order 4 bits (contents of DBq~DB3 when interface data is 
8 bits long) . 



RS 
R/W- 
E 



s 



s 



3.7 

The 
(us 
ini 
(1) 



(2) 



(3) 



(4) 



db, 

DB j 
DB« 



M6> 



(5) 

Bee 
the 



Instruction (IR) 
Write 



Busy Flag (BF) and 
Address Counter (AC) 
Read 



Data register (DR) 
Read 



Fig. 3.1 4-bit Data Transfer Example 



(2) When interface data is 8 bits long, data is transferred using 8 data buses of 

- 

DBq ~DB7. 



Not 



6 HITACHI 



7 Reset Function 

The HD44780 automatically performs initialization (reset) when power is turned on 
(using internal reset circuit). The following instructions are executed in 
initialization: 

(1) Clear display 

The busy flag is kept in the busy state (BF=1) until initialization ends. 
The time is 15ms. 

(2) Function set DL=1 : 8 bits long interface data 

N =0 : 1-line display 

F =0 : 5^7 dot character font 

(3) Display ON /OFF control D =0 : Display OFF 

C =0 : Cursor OFF 
B =0 : Blink OFF 

(4) Entry mode set 1/0=1 : +1 (increment) 

S =0 : No shift 



(5) DD RAM is selected 

Because initialization may not be performed completely depending on the rise time of 
the power supply when it is turned on, pay attention to the following time relationship 




1 m s SI tree i> 1 ms toFF — 1 ms 

t-OFF stipulates the time of power OFF for power supply instantaneous dip or 
when power supply repeats ON and OFF. 

Note: When the above power supply condition is not satisfied, the internal reset 



circuit does not operate normally. In this case, perform the needed 
initialization by sending instructions from MPU after turning the power ON. 
When initialization by the internal reset circuit is not performed normally, 
whether the interface data is 4 bits long or 8 bits long is not clear. 
Therefore, designate 8-bit data length by sending the function set instruction 
twice and then perform the required initialization. (See Chapter 4, Instruction.) 

RS R/W DB 7 DB, DB, DB 4 DB, DB, DB, DB 
00001 1**** 

000 01 1 **** 
When this instruction is sent, the HD44780 enters the 8-bit data length mode 
without fall. 



HITACHI 17 



■■■HI 



m I nHHi ■■ 



4. Instruction 
4.1 Outline 

Two registers of the HD44780, the Instruction Register (IR) and the Data 
Register (DR) only can be controlled by MPU directly. Control information is 
temporarily stored in these registers, prior to internal operation start, to 
allow interface to various types of MPUs which operate in different speeds 
from HD44780 internal operation or to allow interface to peripheral control ICs . 
The HD44780 internal operation is determined by signals sent from the MPU, 
these signals including register selection signals (RS) , read/write signals 
(R/W) and data bus signals (DBq 'DB7) , are called instructions in this paragraph. 
Table 4.1 shows the instructions and the execution time of the instructions. 
Details are explained in the following sections. The instructions can be 
divided into the following 4 types: 

(1) Instructions that designate .the HD44780 functions such as display format, 
data length, etc. 

(2) Instructions that give internal RAM addresses. 

(3) Instructions that perform data transfer with internal RAM. 

(4) Other instructions 

In the normal use, instructions of category (3), which sends display data, is 

used most frequently. However, since the HD44780 internal RAM addresses are 
configured to be automatically incremented (or decremented) by +1 after each 
data write, MPU program load is lessened. Especially, display shift is 
performed concurrently with display data write, and this enables the user to 
develop systems with minimum time and maximum efficiency of programming. 
For explanation of the shift function, refer to Item 6.6. 
When an instruction is being executed (during internal operation) , no 
instruction other than Busy flag/address read instructions is executed. 
Because the Busy flag is set to "1" while an instruction is being executed, 
this must be checked prior to sending an instruction from the MPU. 



18 HITACHI 




■I ■ ■■■^■■H 



Table 4.1 Instructions 



m is 
to 

is 

ol ICs. 
.Is 

ragraph. 
,ns. 



t, 



, is 

are 

ach 

to 



i, 



Instruction 


Code 


Description 


Execution Time 
(when fcp or 
fosc is 250 KHz) 


RS 


R/V, 


DB7 


DB & 


DB5 


DE4 


DB3 


UB2 


DBi 


mo 


Clear 

Display 





























l 


Clears all display and returns 
the cursor to the home 
position (Address 0) . 


82ys— 1.64ms 


Re turn 

Home 


























1 


* 


Returns the cursor to the home 
position (Address 0) . Also 
returns the display being 
shifted to the original 
position. DD RAM contents 
remain unchanged. 


• 

40us — 1.6ms 


Entry 
Mode Set 























1 


I/D 


s 


Sets the cursor move direction 

ulIU Bl'CLll J.CO KJ L 1IU L L VJ Oil 1 1 L 

the display. These operations 
are performed during data 
write and read. 


40ps 


Display 
ON /OFF 
Control 




















1 


D 


c 


B 


Sets ON /OFF of all display (D) 
cursor ON/OFF (C) , and blink of 
cursor position character (B) . 


40ps 


Cursor or 
Display 
Shift 

















1 


s/c 




* 


* 


Moves the cursor and shifts 
the display without changing 
DD RAM contents. 


40ps 












i? 


DL 


N 


F 


* 


* 


Sets interface data length (DL] 
number of display lines (L) 




function - 


n 








fit 












and character font (F) . 


40vs 


Set CG RAM 
Address 











1 


ACG 


Sets the CG RAM address. CG 
RAM data is sent and 
received after this setting. 


40)js 


Set DD RAM 
Address 


u 





1 


Add 


Sets the DD RAM address. DD 
RAM data is sent and 
received after this setting. 


40us 


Read 
Busy Flag 
& Address 





1 


BF 


AC 


Reads Busy flag (BF) indicating 
internal operation is being 
performed and reads address 
counter contents. 


40ys 


DD RAM 


l 





Write Data 


Writes data into DD RAM or 
CG RAM. 


40ps 


Read„Data 
to CG or 








Reads data from DD RAM or 
CG RAM. 


40Ms 




I/D=l : Increment 
I/D=0 : Decrement 
S =1 : Accompanies display 

shift. 
S/C=l:Display shift 
S/C=0: Cursor move 
R/L=l: Shift to the right. 
R/L=0: Shifts to the left. 
DL=1: 8 bits, DL=0: 4 bits 
N=l: 2 lines, N=0 : 1 line 
F=l:5><10 dots, F=0:5*7 dots 
BF=1: Internally operating 
BF=0:Can accept instruction 


DD RAM:Display data RAM 

CG RAM:Character generator RAM 

ACG'^G RAM address 

A D n:DD RAM address. 

Corresponds to cursor 

address . 
AC: Address counter used for 

both of DD and CG RAM 

address. 


execution time 
changes when 
frequency 
changes . 

(Example) 

When fcp or 

fosc is 270 KHz: 

250 

40ps x |^ = 3 7ys 



* Dont' care 



HITACHI 19 



4.2 Description of Details 



(1) Clear Display 


RS 


H. * 


DH? 
















Code 





























1 



Writes space code "20" (hexadecimal) into all the DD RAM addresses. 
• The cursor returns to Address (AnD="00") and display, if it has been shifted, 
returns to the original position. In other words, display disappears and the 
cursor goes to the left edge of the display (the first line if 2 lines are 
displayed) . 

(2) Return Home RS R/W D B 7 - — D*» 



Code 



























1 


* 



* ( Do n't Care) 



Returns the cursor to Address (Add="00") and display, if it has been shifted, 
to the original position. The DD RAM contents remain unchanged. 
(3) Entry Mode Set 



RS R/W DB 7 



— DB„ 



Code 
























1 


I/O 


s 



I/D: Increments (I/D=l) or decrements (I/D=0) the DD RAM address by one upon 
writing into or reading from the DD RAM a character code. The cursor 
moves to the right when incremented by one. The same applies to writing 
and reading of CG RAM. 

S : Shifts the entire display to either the right or the left when S is 1; 

to the left when I/D=l and to the right when I/D=0. Therefore, the cursor 
looks as if it stood still with the display only moved. Display is not 
shifted when reading from the DD RAM. 
Display is not shifted when S=0. 



(4) Display ON/ OFF Control 

RS R/ft'DB, 



DB . 



Code 





















1 


D 


C 


B 



























Display is turned ON when D=l and OFF when D=0. When display is turned 
off due to D=0, the display data remains in the DD RAM and it can be 
displayed immediately by setting D=l. 

The cursor is displayed when C=l and not displayed when C=0 . 
Even if the cursor disappears, function of I/D, etc. does not change 
during display data write. The cursor is displayed using 5 dots in the 8th 
line when the 5 x 7 dot character font is selected and in the 11th line 
when 5xl0dot character font is selected. 

The character residing at the cursor position blinks when B=l. The blink 
is done by switching between all the black dots and display characters at 
0.4 second interval. The cursor and the blink can be set concurrently. 



20 HITACH! 



, shifted, 
and the 
are 



shifted, 



upon 
;or 

iting 



8 th 



ink 
at 





Cursor 

Alternative Display 
5X7 Dot 5x10 Dot 

Character Font Character Font 

Ca) Cursor Display ( b ) Blink Display 

Example Example 
(5) Cursor or Display Shift 

RS R/W DBt — ■ — — — DBo 



Code 

















l 


s/c 


R/L 


* 


* 



















( Do n'1 Care) 



Shifts the cursor position or display to the right and the left without 
writing or reading the display data. This function is used for correction 
or search of display. 
S/C R/L • 

Shifts the cursor position to the left. (AC is decremented by one.) 
Shifts the cursor position to the right. (AC is incremented by one.) 
Shifts the entire display to the left. The cursor follows the display 
shift. 

Shifts the entire display to the right. The cursor follows the 
display shift. 







RS 


R/W 


DB? 














DBo 


cursor 
























not 


Code 














1 


DL 


N 


F 


* 


* 























(Don't Care) 

DL : Sets interface data length. Data is sent or received in 8 bit length 
(DB7~DBq) when DL=1 and A bit length (DB 7 ~DB4> when DL=0 . 
When 4 bit length is selected, data must be sent or received twice". 

N : Sets number of display lines. 

F : Sets character font. 



N F 


Mo. of 
Display Lines 


i 

Character Font 


Duty Factor 


1 1 

Remarks 





1 


5x7 dots 


1/8 




1 


1 


5x10 dots 


1/11 




1 * 


2 


5x7 dots 


1/16 


Cannot display 2 lines with 
5x10 dot character font. 



(7) 



* (Don't Care) 
Set CG RAM Address 





RS 


R/W 


DB 7 












DB 


Code 











1 


A 


A 


A 


A 


A 


A 



■►Higher Order Lower Order-- 
Bits Bits 

Sets the CG RAM address in a binary number of AAAAAA to the address counter, 
and data is written or read from the MPU related to the CG RAM after this. 



HITACHI 21 



(8) Set DD RAtt Address 



HS R/w i)B 7 











1 


A- 


A 


A 


A 


A 


A 


A 


Code 



















Higher Order Lower Oider^ 

• Bit? Bits 

Sets the DD RAM address in a binary number of ANAAAAAA to the address counter, 
and data is written or read from the MPU related to the DD RAM after this. 
However, when N=0 (1-line display), A N AAAAAA is "00" ~ "4F" (hexadecimal). 

When N=l (2-line display), A N AAAAAA is "00"~"27" (hexadecimal) for 
the first line, and "40"~"67" (hexadecimal) for the second line. 



(9) 



Code 



RS 


R/W" 
















DB 



















1 


BF 


A 


A 


A 


A 


A 


A 


A 



.Higher Order Lower Order _ 

Bits Bits 
Reads Busy Flag (BF) that indicates the system is internally operating on an 

instruction received before. When BF=1, it indicates that internal operation 

is going on and the next instruction is not accepted until BF is set to "0". 

Check the BF status before the next write operation. 

At the same time, this value of the address counter expressed in a binary 
number of AAAAAA. The address counter is used by both of CG and DD RAM address, 
and its value is determined by the previous instruction. 
Address contents are the same as Items (7) and (8). 
(10) Write Data to CG or DD RAM 





— RS 


R/W 


I>B; 














DB 


Code 


1 





D 


D 


D 


D 


D 


D 


D 


D 



Bits Bits 
Writes binary 8 bit data DDDDDDDD to the CG or the DD RAM. 

Whether the CG or the DD RAM is to be written is determined by the previous 
designation (CG RAM address setting or DD RAM address setting). After write, 
the address is automatically incremented or decremented by one according to 
entry mode. Display shift also follows the entry mode. 
(11) Read Data from CG or DD RAM 





RS 


R/W 


DB 7 














DB 


Code 


l 


1 


D 


D 


D 


D 


D 


D 


D 


D 



Higher Order 

Bits Bits 
Reads binary 8 bit data DDDDDDDD from the CG or the DD RAM. 

Whether the CG RAM or the DD RAM is to be read is determined by the previous 
designation. Prior to inputting this read instruction, either the CG RAM 
address set instruction or the DD RAM address set instruction must be executed. 
If it is not done, the first read data becomes invalid, and data of the next 
address is read normally from the second read. 

After read, the address is automatically incremented or decremented by one 
according to the entry mode. However, display shift is not performed 
regardless of entry mode types. 
22 HITACHI 



5. Electrical Characteristics 
5.1 Absolute Maximum Ratings 



Item 


Symbol 


Limit 


Unit 


Note 


Power Supply Voltage (1) 


VCC 


-0.3 to +7.0 


V 




Power Supply Voltage (2) 


VI to V5 


VCC- 13. 5 to VCC+0. 3 


V 


3 


Input Voltage 


VT 


-0. 3 to VCC+0. 3 


V 




Operating Tempertaure 


Topr 


-20 to +75 


°C 




Storage Tempertaure 


Tstg 


-55 to +125 


°C 





Note 1: When LSI's are used beyond the absolute maximum rating, LSI's may 
be permanently destroyed. Use under the electrical characteristic 
conditions is strongly recommended for normal operation. The use 
beyond these conditions, cause LSI's malfunction and at the same 
time undesirable effects on the reliability of the LSI's. 

Note 2: All voltage values are referenced to GND=0V. 

Note 3: Apply to VI to V5. Must keep the relation of VI > V2 SV3 S VA 2; V5 

(high* — — >low) 



5.2 Electrical Characteristics 

VCO5V+10Z 
Ta— 20 to +75°C 



item 


Svmbol 


Test Condition 


Limit 


Unit 


No t e 


tain 


typ 


max 


Input "High" Voltage 


VIH 




2.0 




VCC 


V 


2 


Input "Lou" Voltage 


VIL 




- 0. 3 




0. 8 


V 


2 


Outnut "Hieh" Vol face ( 1) ( TTL) 


V0H1 


- IOH=0. 205mA 


2. 4 


- 




V 


3 


Output "Low" Voltage (1)(TTL) 


V0L1 


LOL- 1.6mA 






n 4 


V 


3 


f Air nn r " Hi ph" Vn 1 r aop ( ?} ( CMOS'! 


V0H2 


- TOh«fi flimA 


0. 9VCC 






y 


i, 


fnirnnr "Ir^u" Unl raopC ?UTMOS\ 

\Ai L|'UL iXJ w VUJ. Ld^c V ^ / V ivJ tD / 


V0L2 








n wire 


y 




Yrr i up t Vn 1 faop cppnffi noi C!(iMl 

UL J. V C I tUl i-OEC IVC Oi_C 1IU 1 11 1 \ V> Wl i y 


Vd 1 


ld=0 InA 






1 


V 




Yir i upr Vn. 1 faop Hp crpnH i no ( SFfi^ 


Vd2 


ld=0 OlnA 






0. 2 


v 




Input Leakage Current 


IIL 


Vin=0 to VCC 






1 


UA 


5 


Pull up MOS Current 


-IP 


VCC=5V 


2 


10 


20 


PA 




Power Supply Current 


ICC1 


Ceramic Filter 
Oscillation 




0.4 


1.0 


mA 


6 


Power Supply Current (2) 


1CC2 


Rf Oscillation, 
External Clock 
Operation 




0. 2 


0. 5 


mA 


6 


External Clock Operation 
External Clock Frequency 


f cp 




125 


250 


300 


kHz 


7 


External Clock Duty 


Duty 




45 


50 


55 


% 


7 


External Clock Rise Time 


Tr cp 








0.2 


ps 


7 


External Clock Fall Time 


Tfcp 








0.2 


ys 


7 


Internal Clock Operation(Rf Oscillation) 

Clock Oscillation Frequency fosc ~~| Rf = 91kQ+2Z 190 | 250 \ 310~| kHz | 8 


Internal Clock Operation(Ceramic Filter Oscillation) 

Clock Oscillation Frequency \~ fosc pCeramic Filter \~ 245 ^50"! 255 \~kHz~\ 9 



24 HITACHI 



Note 1: The following shows the configurations of 1/0 terminals except 
liquid crystal display output. 
•Figure of Input Terminal 
Applicable Terminals : RS, R/K, E 



^ |pJ PMOS 



(Pull Up MOS) 



r-| pJ PMOS 



•^j] NM ° S 



•Figure of Output Terminal 
Applicable Terminals : CL^, CL2, M, D 



•cc 



•Figure of 
Appllr.a h . 



I/O Terminal 



v ( Pul1 U P) 
cc k MOS ; 

^ jilpMOS |i 



Circuit) 



PMOS 



Enable 



P-l NMOS 



2 




.Output Circuit. 
(Tristate) 



Note 2: Applies to the input terminals and the I/O terminals. 
Note 3: Applies to the I/O terminals. 
Note 4: Applies to the output terminals. 

Note 5: Current that flows through pull-up MOS's and output drive MOS ' s is 
excluded. 

Note 6: Current that flows through pull-up MOS ' a is excluded. With CMOS, when 
input is in the intermediate level, excessive current flows through the 
input circuit to the power supply. In order to avoid this, input level 
must be settled high or low. 



HITACHI 25 



Note 7: Applies to the external clock operation. 



[ Oscillation f - 
Open 



OSC, 



OSC 



Th 



Tl 









0.7 V M 

05V CC - 

o.«v ee / 


■ L V 
r \ 







Du ty 



Th 
Th + Tl 



x l o % 



t,. 



t r«p 



Note 8: Applies to the internal oscillator operation when oscillation resistor 
Rf is used. 




Since the oscillation frequency varies depending on capacity of OSC-^ and 
OSC 2 terminals, length of the wirings for these terminals should be 
minimized . 

Note 9: Applies to the internal oscillator operation when a ceramic filter is used 



m 



c, 



T 

CD 

1\ 



c, 



OSC, 



OSC 



Ceramic Filter : c B S 2 5 o A (Murata) 
Rf : 1 UO. ±10% 
C, :100 P F±10% 
C :100 P F±10% 



Ceramic Filter 



HITACHI 



5.3 Timing Characteristics (V cc = 5V 1107c. Ta = -20 to +75°C) 



I tern 


Symbol 


Test Conditions 


Limi t 


Unit 


min 


typ 


max 


Enable Cycle Time 


'eye 


Fig. 5.1, Fig. 5. 2 


3.0 






Ms 


Enable Pulse Width 


PW EH 


Fig. 5.1, Fig. 5. 2 


1.8 


_ 


__ 


Ms 


Enable Rise /Fall Time 


tEr-tEf 


Fig. 5.1, Fig. 5. 2 






2.0 


Ms 


Address Set-up Time 


tAS 


Fig. 5.1, Fig. 5. 2 


0.9 






Ms 


Data Delay Time 


tDDR 


Fig. 5. 2 






0.9 


ys 


Data Set-up Time 


tDSW 


Fig. 5.1 


0.9 






Ms 


Hold Time 


*H 


Fig. 5.1, Fig. 5. 2 


0.9 






PS 


Clock Pulse Width("High"Level) 


km 


Fig. 5. 3 


1.5 






Ms 


Clock Pulse Width ("Low"Level) 


'CWL 


Fig. 5. 3 


1.5 






Ms 


Clock Set-up Time 


tcsu 


Fig. 5. 3 


1.5 






MS 


Data Set-up Time 


tsu 


Fig. 5. 3 


1.5 






MS 


Data Hold Time 


C DH 


Fig. 5. 3 


1.5 






MS 


M Delay Time 


tDM 


Fig. 5. 3 


-1.5 




1.5 


Ms 



Write Operation 



RS 



R/W 



DBo-DB, 



\y 20V 

/ ^osv 



8V 



PW t 



- f 2.0V 
0.8V 



2.0V \f 



20V\ t 



2.0V 
0.8V 
tnew 



L 



ta 



8V 



Valid 

v A Data 



X! 



ov 

8V 



f 



Fig. 5.1 Writing Data from MPU to HD44780 



HITACHI 27 




Kow to Use HD44780 
. 1 Interface to MPU 
(1) Interface to 8-bit MPU 

RS 



f 



r~\ r~\ j \ r~\ r~\ 



Internal- 



Internal Operation 



1 



No 



Instruction L Busy Flag Busy Flag Busy Flag Instruction 
Write Check . Check Check Write 

IR7: Instruction 7th Bit I 

Fig. 6.1 An Example of Busy Flag Check Timing Sequence 

Since the HD44780 cannot be directly connected to MPU address bus and data bus 
PIA or I/O port (in the case of single chip microcomputer) is needed as an interface 
device. Input and output of the interface device is TTL compatible. 
Fig. 6.2 shows a circuit example. 



In the example,. PB 



' 



■PB, 



o -the data bus DBq ~ DB^and PAq~PA 2 are 
connected to E, R/W and RS respectively. 

Attention must be paid to the timing relation between E and other signals when 
reading ot writing data using PIA as* an interface. 



HD468B00 



A,j 
A,« 

A 13 

A i 

Ac 
R/W 
VMA 

DB ~DB 7 



cs, 

OS, 
CS 
RS, 
RS o 
R/W 
E 

Do-D, 



PA 2 

PA, 

PAo 
HD+68B21 

PBo-PBt 



RS 



R/W 



COM,- 
COM,, 



HD44780 



SEG,~ 
SEG 40 



DB — DB 7 



1 6 



40 



Connected 
> to Liquid 
Crystal 
Display 



HD468BO0 : 8 bit CPU 

Fig. 6.2 An Example of Interface to HD468B00 Using PIA (HD468B21) 



HITACHI 29 



(2) Interface to A-bit MPU 

The HDAA780 can be connected to A-bit MPU through A-bit MPU I/O port. 
If the I/O port has enough bits, data can be transfered in 8-bit length, but 
if not in two operations of A bits each (with designation of interface data 
length for A bits). In such case, the timing sequence becomes a little 
complicated (See Fig. 6.3). 

Fig. 6. A shows an interface example to HMCSA3C . 

Note that 2 cycles are needed for busy flag check as well as data transfer. 
A-bit operation is selected by program. 



ES 



R/W 



f 



rvr\ rvr\ n_r\ rvry 

I Internal 1 J~ 

Opera tion No 



Internal 

Instruction l Busy Flag l Busy Flag Instruction 
Write Check Check Write 

Note : IR7, IR3 : Instruction 7th bit, 3rd bit 

■ 

AC 3 rAddres Counter 3rd bit 

Fig. 6.3 An Example of A-bit Data Transfer Timing Sequence 



D„ 




RS 














""^ COM,, 
E HD+4780 


) 6 

— / - 








HMCS 






*8C D,S 












4,0 

— A— 




* 




Rio — Ris 




DB,~DB, SEG «o 






~ / - 





HMCS43C : Hitachi 4 bit single chip microcomputer 
Fig. 6. A An Example of Interface to HMCSA3C 



Connected 
to Liquid 
Crystal 
Display 



30 HITACHI 



6.2 Interface to Liquid Crystal Display 
(1) Character Font and Number of Lines 

The HD44780 can perform 2 types of display, 5*7 dots and 5*10 dots as 
character font, with a cursor on each of them. Number of display lines is 
up to 2 lines with 5x7 dots and 1 line with 5><10 dots. Therefore, number of 
common signals available are the following three types: 



Number of 
Lines 


Character Font 


Number of 
Common Signals 


Duty 
Factor 


1 


5x7 dots + Cursor 


8 


1/8 


1 


5x10 dots + Cursor 


11 


1/11 


2 


5x7 dots + Cursor 


16 


1/16 



(2) 



Number of lines and font types can be selected by program, 
(refer to Chapter 4, Instruction) 

Connection to HD44780 and Liquid Crystal Display 
Fig. 6.5 (1) and (2) show connection examples. 



COMi 



HD44780 



COM» 



SEGi 



SEG40 



Liquid Crystal 
Display Panel 
(8 characters 
xl line) 



(a) An Example of 5x7 dot, 8 character x 1 line Display 

(1/4 Bias, 1/8 Duty) 



COM, 



COM,, 



HD+4780 



SEG, 



SEG« 



J 



Liquid Crystal 
Display Panel 
(8 characters 
xl line) 




(b) An Example of 5x10 dot, 8 character x 1 line Display 

(1/4 Bias, 1/11 Duty) 

Fig. 6.5 (1) Examples of Connection to HD44780 and Liquid Crystal Display 



HITACHI 31 




Liquid Crystal 
Display Panel 
(8 characters 
x2 lines) 



(c) An Example of 5><7 dot, 8 character x 2 line Display 

(1/5 Bias, 1/16 Duty) 
Fig. 6.5 (2) An example of Connection to HD44780 and Liquid Crystal Display 

Since 5 signal lines at the SEG can display one digit, one HD44780 can 
display up to 8 digits in the case of 1-line display and 16 digits in the 

. -TanjM 

case of 2-line display. 

In the examples of Fig. 6.5 (a) and (b) , there are some unused common signal 
terminals, non-selection waveforms which always output. When there are unused 
extra scanning lines in the liquid crystal display panel, undesirable influence 
due to cross-talk in the floating state can be avoided by connecting the extra 
scanning lines these common signal terminals. 



COM i 



COM. 



COM. 



HD44780 



SEG, 



SEG 40 



1 4 



5 X 7 dot, 8 character * 1 line Display (1/4 Bias, 1/8 Duty) 
Fig. 6.6 An Example of Using COM9 for Avoiding Cross-talk of the Unneeded 
Scanning Line 



32 HITACHI 



Power Supply for Liquid Crystal Display Drive 

Various levels of voltage must be applied to the HD44780 terminals V-^ to V5 
in order to obtain drive waveforms of liquid crystal display. These voltages 
must be changed according to duty factors. Table 6.1 shows the relation. 
Table 6.1 Duty Factor and Power Supply for Liquid Crystal Display Drive 

Duty Factor 





V,. Vn 


% 


^ - 
Power Supply, 


n 


H 


v, 


V — 'A V 

* CC ^ LCD 


v — u v 

CC /5 v LCD 


v 2 


v cc — % V LCD 


V C c - KV LCD 


v 3 




V — *AV 

* CC ^ 'LCD 


v 4 


V cc % V LCD 




v 5 


V cc — V lcD 





V LCD 8 ive s peak values of liquid crystal display drive waveforms. 

Each voltages can be given by resistance dividing as shown in Fig. 6.8. 



\fcc (+5 V) 





V ccf 
V. 



-5V 



R 
K 
R 
R 
R 



(a) 1/4 Bias 

(1/8, 1/11 Duty) 



(b) 1/5 Bias 

(1/16 Duty) 



Fig. 6.8 Drive Voltage Supply Example 



HITACHI 33 



(3) Connection of Changed Matrix Layout 

In the preceding examples, number of lines were corresponded to scanning lines. 
The following types of displays are possible by changing layout of the matrix 
configuration in the liquid crystal display panel. 



COM, 



COM, 



SEG, 



HD++780 



SEG 40 
COM, 



COM,, 



=9= 



(a) An Example of 5x7 dot, 16 character * 1 line Display 

(1/5 Bias, 1/16 Duty) 



SEG, 

SEG 2 , 
COM, 



COM. 



HD++780 



SEGj, 



S EG«o 



(b) An Example of 5x7 dot, 4 character x 2 line Display 

(1/4 Bias, 1/8 Duty) 
Fig. 6.7 A Display Example of Changed Matrix Layout 

In either case, the change is only on the layout and display characteristics and 
number of display characters of liquid crystal are dependent on the number of 
common signals (or duty factor) . Note that the display data RAM (DD RAM) addresses 
for 8 characters x 2 lines and 16 characters x i ii ne are the same as shown in 
Fig. 6.5. 



34 HITACHI 



R 
c 
i 
d 
o 

i 

c 

■y 
i 
1 
i 



I - * ■■■ | 




Resistance value is determined in consideration of operation margin and power 
consumption. Since liquid crystal display load is capacitive, drive waveform 
itself is distorted by charge/discharge current when the liquid crystal display 
drive waveform is applied. To minimize the distortion, the resistance value 
must be made smaller, but this increases the current flown through the dividing 
resistors causing higher power consumption. 

Since larger liquid crystal display panels have larger capacitance, resistance 
value must be made smaller. 

Adding capacitors in parallel to resistors, as shown in Fig. 6.9, is effective 
to improve charge/discharge distortions. However, there is a limit in the 
effect. Level shift occurs and operation margin cannot be improved even if 
attempts are made in reducing power consumption with large resistance and in 
improving waveform distortion with large capacitance. 




1 



With C 



Without C 



Level shift occurs 
when C and R is 
too large. 

c 



-sv 



Fig. 6.9 A Capacitor Connection Example for Improvement of Distortion 
of Liquid Crystal Display Drive Waveform 



Since the liquid crystal display load is in a matrix configuration, paths of the 
charge/discharge current flown through load are complicated. Furthermore, 
since the current changes by display conditions, resistance values cannot be 
determined simply from liquid crystal display load capacitance. Resistance 
values must be determined experimentally in consideration of power consumption 
requiremant of the device into which the liquid crystal display is incorporated. 
Generally, R=l ~ lOkQ and VR=5 ~50kfi are used without using capacitors. 
Capacitors, if they are used, are usually of O.lpF or less. 



HITACHI 35 




6. A Liquid Crystal Display Drive Waveform 

Examples of voltage levels and liquid crystal display drive waveforms are 
shown below. 



(a) Example of 

Liquid Crystal Display 
Drive Waveform 
(1/4 Bias, 

1/8 Duty) 



com, - BHBOD- 

co Mj — oaooa- 
com s — oacog- 
com 4 — Daaao- 

com,— DaODH- 

c °m.— oacoa- 

com, — HQC30: .} 
com, — BBESQBI 



o o o o o 
u a u; u 

CO CO CO CO CO 



COM, 



V, 

v,(v s ) 

v 4 

v, 

v 

* CC 

v, 

COM, V,(Vj) 

v, 

V, 

SEG, V,(V,) 
V« 

v 3 

Vcc 
V, 

SEG, V,(V 3 ) 

V« 

V, 



I 1 I » I 3 | * | | . | 1 | 



1 


1 


















































1 


1 



Vj — v cc 
v,( v,)=v cc - 

V = V - 

v. =v cc - 



V4V lCD 
% v LCD 



KV, 



-KV, 



LCD 



COM, - SEG, 
.Selected . 
Waveform 



K V LC D 

COM 2 - SEG, 
.Non-selected. _ ^Vd 
* Waveform V,^,, 



































































1 





v. 
v. 



Fig. 6.10 Example of Liquid Crystal Display Drive Waveform d) 



36 HITACHI 



(b) Example of Liquid Crystal Display Drive Waveform (1/5 Bias, 1/16 Duty) 



COM, 



COM," 

com, — DHOOfl — 
com, — OHOOfl - 
com, — QfiBBO- 
coM,_ □BDOD- 
C0M » — DHDDB— 

COM,— 

com, - 



v, 

Vf 

v, 

v 4 - 

v.- 




v, 
v 2 

COM 2 v 

v. 

v, 



com, — DEBHO- 
com b — BDOOfi— 
com„ — DOQOH- 
com e — DOOBCh 
com u — DOBOZr- 

COM B 
COM, 



c5 o o o" o 

Cd U M td Cd 

W to K> K> tr> 



S EG, 



v, 

V.- 
v, 

v, 




SEG, 



V, 
V 2 

v, 
v 4 

v, 

Vu:n 



v, = v cc 
v t = v cc 



" ^ V LCD 

" v LCD 



COM, - S EG, 

.Selected . 
*■ Waveform"^ 



( 



COM 2 -SEG, 
Non-selected. 



Waveform' 



**M Vlcd 

-Vlcd ■ 

Vlcd 
HVlcd 
XVlcd 
-KVlcd 
-JsVlcd 
-Vlcd 



1 


1 














































































1 





Mill 



































1 





















































Fig. 6.10 Example of Liquid Crystal Display Drive Waveform (2) 



HITACHI 37 



6.5 Connection with Driver LSI HD44100 

Number of display digits can be increased by externally connecting a liquid 
crystal display driver LSI HD44100 to the HD44780. Fig. 6.11 shows the HD44100 
block diagram. 

The HD44100 consists of shift registers, latch circuits and liquid crystal 
display drive circuits. The HD44100 is the general purpose liquid crystal 
display driver LSI to which any bias balues can be set by externally applying 
supply voltage. Its internal circuits are divided into 2 channels of 20 circuits 
each and they can be used separately for common and segment signals. The shift 
registers have bidirectional function allowing design flexibility. 
Table 6.2 shows I/O signal description. 

When connected to the HD44780, the HD44100 is used as segment signal driver. 
The HD44100 can be connected to the HD44780 directly since CLi, CL2, M and D 
signals and power for liquid crystal display drive are supplied by the HD44780. 
Fig. 6.12 shows a connection example. 

Caution : Connection of voltage supply terminals V± through V2 for liquid crystal 
display drive is complicated. 

Up to 9 units of the HD44100 can be connected in the case of 1-line display 
(duty factor 1/8 or 1/11) and up to 4 units in the case of 2-line display 
(duty factor 1/16) . The limit is due to maximum display digit numbers for the 
HD44780 being 80 characters because of RAM size. The connection method shown 
in Fig. 6.12 remains unchanged for both of 1-line and 2-line display or for both 
of 5x7 and 5x10 dot character fonts. 



38 HITACHI 



Y, - 



Y« 



V..V, 
V..V, 

M 
C L, 

DL, 
CL, 



FCS- 

V„V, . 
V,,V. 



Liquid Crystal Display Driver 
1 20 ' 



20-bit Latch 



• 2 



20-bit Bidirectional 

Shift Register 



Channel 1 



Data Selector 



Data Selector 



20-bit Bidirectional 

Shift Register 



JJ20 



20-bit Latch 



Liquid Crystal Display Driver 




SHL, 
DR, 

DR, 
SHL, 



Channel 2 



Fig. 6.11 HD44100 Block Diagram 

Table 6.2 HDA4100 Terminal Function Description 



Signal Name 


I/O 


Function 


Yl^Y 40 


Output 


Liquid crystal display drive output. Y-j^ Y20 and Y 2 1 Y40 
correspond to Channels 1 and 2, respectively. 


Vi~ V6 


Input 


Power supply for liquid crystal display drive. and V 2 give 
selection voltage, V3 and V4 give non-selection voltage of 
Channel 1, and V5 and give non-selection voltage of Channel 2. 


SHLl, SHL 2 


Input 


Signals to determine shift direction of bidirectional shift 
registers. When SHL^ and SHL 2 are "Low", DLi and DL2 are inputs 
and DRi and DR2 are outputs . 


DLi, DL 2 , 
DRl, DR 2 


Input/ 
Output 


Data input/output of shift registers 


M 


Input 


Signal to convert liquid crystal display drive output to AC. 
V1/V2, V3/V4 and V5/V6 are output alternatively. 


CL-,, CL2 


Input 


Data shift clock (CL2) and latch clock (CLl) 


FCS 


Input 


Mode selection signal for Channel 2. It can be used for segment 
signal drive when FCS is "Low" and for common signal drive when 
FCS is "High". Channel 1 remains unchanged 
(It is for segment signal)- 



HITACHI 39 




6.6 Correspondence Example of Instructions and Display 

(1) 8-bit Operation, 8-digit x 1-line Display 

Table 6.3 shows a display example of 8-digit * 1-line in 8-bit operation. 

The HD44780 functions must be set by Function Set prior to display. 

Since display data RAM can store data for 80 chatacters, as explained before, 

the RAM can be used to display like lightning board when combined with display 

shift operation. 

Since display shift operation changes the display position only and the DD RAM 
contents remain unchanged, display data entered first can be output when 
return home operation is performed. 

(2) 4-bit operation, 8-digit x 1-line display 

Function set by a program is needed prior to 4-bit operation. Table 6.4 shows 
an example. When power is turned on, 8-bit operation is automatically selected 
and the first write is performed as 8-bit operation. At this time, since 
nothing is connected to DBo — DB3, rewrite is required. However, since one 
operation completes in two accesses in the case of 4-bit operation, rewrite 
is needed as function (see Table 6.4) 
Thus, DB4-~DB7 of function set are written twice. 

(3) . 8-bit Operation , -fi -digits X-2-line display 

For 2-line display, the cursor moves from the first line to the second line 
automatically after write into the 40th digit of the 1st line is finished. 
Therefore, if there are only 8 digits in the first line, the DD RAM address 
must be set again after completion of the 8th digit, (see Table 6.5) 
Note that the first and second lines of the display shift are performed. 
In the example, display shift is performed when the cursor is on the second 
line. However, if shift operation is performed when the cursor is on the 
first line, both the first and the second lines move concurrently. When 
shift is repeated, display of the second line does not move to the first line, 
but the same display only moves in each line many times. 



HITACHI 41 



Table 6.3 8-bit Operation, 8-digit * 1-line Display 



Instruction 


Display 


Operation 


Power Supply ON 
(Internal Reset Circuit) 


1 


Initialized. No display appears. 


Function Set 

15". ?AJ IT-7 ■ DBO 

1 1 * * 




Sets to 8-bit operation and selects 1-line 
display and 5*7 dot character font. 


Display ON /OFF Control 
0000001110 




Turns on display and cursor. All display is 
in space mode because of initialization. 


bntry Mode Set 
0000000110 


1 


Sets mode to increment the address by one 
and to shift the cursor to the right at the 
time of write to the DD/CG RAM. 
Display is not shifted. 


Write Data to CG RAM/ 

DD RAM 
100100 1 00 


H _ 


Write "H". The DD RAM has already been 
selected by the initialization performed 
when the power is turned on. The cursor is 
incremented by one and shifted to the right. 


Wiite Data to CG/RAM 

DD RAM 
10C1 01001 


1 "I- | 


Wrlt£S 


1 


i 

i 
t 
I 




Write Data to CG/RAM 

DD RAM 
1001001001 


HITACHI- 


Writes "I". 


Entrv Mode Set 
0000000111 


IJ T T A r* U T 
HI 1ACH1 — 


Sets mode for di ^ulav «="h -i ft- at trip timp nf~ 
write. 


Write Data to CG RAM/ 

DD RAM 
1 1 1)000 


I T A C H I _ 


Writes "space". 


Write Data to CG RAM/ 

DD RAM 
1001001101 


1 T A C H I M _ 


Writes "M" . 


! 


J 
i 




Write Data to CG RAM/ 

DD RAM 
1001001111 


MICROKO — 


Writes "0". 


Cursor or Display Shift 
00000100** 


i 1 

| MICROKO 


Shifts only the cursor position to the left. 


uuiaor u r jjifap j. ay ouii l 
00000100** 


MICROKO 


Shifts only the cursor position to the left. 


Write Data to CG RAM/ 

DD RAM 
1001000011 


I C R O C O 


Writes "C" (correction). 

The display moves to the left. 


Cursor or Display Shift 
00000111** 


M I C R O C O 


Shifts the display and cursor position 
to the right. 


Cursor or Display Shift 
1 1 -* 


| M I C R O C O _ 


Shifts only the cursor position to the right. 


Write Data to CG RAM/ 

DD RAM 
1001001101 


I C R C O M _ 


Writes "M". 


Return Home 
0000000010 


HITACHI 


Returns both of the display and cursor to 
the original position (Address 0). 



42 HITACHI 



Table 6.4 4-bit Operation, 8-digit 1-line Display Example 



Instruction 


Display 


Operation 


Power Supply ON 
v.intemaj. Keset uircun^ 


1 1 


Initialized. No display appears. 


Function Set 
XS R/W VDB7 -DBA 
1 


1 1 


Sets to 4-bit operation. In this case, 
operation is handled as 8 bits by initiali- 
zation, and only this instruction completes 
with one write. 


Function Set 
D 1 
* * 


1 


Sets 4-bit operation and selects 1-line 
display and 5x7 dot character font. 4-bit 
operation starts from this point on and 
resetting is needed. 


Display ON/ OFF Control 

1110 




Turns on display and cursor. All display 
is in space mode because of initialization. 


Entry Mode Set 

1 1 


1 1 


Sets mode to increment the address by one 
and to shift the cursor to the right at the 
time of write to the DD/CG RAM . 
Display is not shifted. 


Write Data to CG RAM/ 

DD RAM 

10 10 
10 10 


IB- ' 


Writes "H". 

The cursor is incremented by one and shifts 
to the right. 



Hereafter, control is the same as 8-bit opers 



HITACHI 43 



Table 6.5 8-bit Operation, 8-digit * 2-line Display Example 



Instruction 


Display 


Operation 


Power Supply ON 
(Internal Reset Circuit) 






Initialized. No display appears. 


Function Set 

RS R/W IB7 — -"DBq 

011110** 






Sets to 8-bit operation and selects 2-line 
display and 5><7 dot character font. 


Display ON /OFF Control 
0000001110 






Turns on display and cursor. All display is 
in space mode because of initialization. 


Entry Mode Set 
0000000110 






Sets mode to increment the address by one 
and to shift the cursor to the right at the 
time of write to the DD/CG RAM. 
Display is not shifted. 


Write Data to CG RAM/ 

DD RAM 
1001001000 


H _ 




Writes "H". The DD RAM has already been 
selected by the initialization performed 
when the power is turned on. The cursor is 
incremented by one and shifted to the right. 


1 

1 

1 


1 




Write Data to CG RAM/ 

DD RAM 
1001001 1 


H I TACHI_ 




Writes "I". 


bet uu kaw Aaaress 

0011000000 


HITACHI 




bets kati aaaress so tnat tne cursor is 
positioned at the head of 2nd line. 


Write Data to CG RAM/ 

DD RAM 
1001001101 


HITACHI 

M _ 




Writes "M". 


! 
1 

1 


1 
1 

1 

1 




Write Data to CG RAM/ 

DD RAM 
1001001111 


HITACHI 
M I C R C O _ 




Writes "0". 


Entry Mode Set 
0000000111 


HITACHI 
M I C R C O _ 




Sets mode for display shift at the time of 
write . 


Write Data to CG RAM/ 

DD RAM 
1001001101 


I T A C H I 

I C R O C O M _ 




Writes "M" . Display is shifted to the right. 
The First line's and the second line's shift 
are operated at the same time. 








Return Home 
0000000010 


HITACHI 
M I C R O C M 




Returns both of the display and cursor to 
the original position (Address 0) . 



44 HITACHI 




■ 



■i 



7. Appendix 

Specification of HD44100 

(1) Absolute Maximum Ratings 



ine 



y is 



ne 
the 



3 

is 

-ght . 



Item 


Symbol 


Limit 


Unit 


Power Supply Voltage (1) 


VCC 


-0.3 to +7.0 


V 


Power Supply Voltage (2) 


Vee.Vl to V6 


VCC- 13. 5 to VCC+0. 3 


V 


Input Voltage 


VT 


-0. 3 to VCC+0. 3 


V 


Operating Tempertaure 


Topr 


-20 to +75 


°c 


Storage Tempertaure 


Tstg 


-55 to +125 


°c 



Note 1: When LSI's are used beyond the absolute maximum rating, LSI's may 
be permanently destroyed. Use under the electrical characteristic 
conditions is strongly recommended for normal operation. The use 
beyond these conditions, cause LSI's malfunction and at the 
time undesirable effects on the reliability of the LSI's. 

Note 2: All voltage values are referenced to GND=0V. 



(2) Electrical Characteristics 

(VCC=5V+10%, Vee, VI to V6=- 4 to -6 



Ta— 10 to +70°C) 



Item 


Synbol 


min 


typ 


max 


Unit 


Note 


Input "High" Voltage 


VIH 


o. 7vcd 






V 


(1) 


Input "Low" Voltage 


VIL 






0. 3VCC 


V 


(1) 


Output "High" Voltage(- I0H=0.4mA) 


VOH 


VCC- 0.4 


- 




V 


U) 


Output "Low" Voltage (10L=O.AmA) 


VOL 






0. 4 


V 




Y^L-to i40 Driver .Voltage Descending 


Vdl 






1. 1 


V 




Vd2 






1.5 


V 




Input Leakage Frequency 


+IIL 






5.0 


A 




Power Supply Current 

Logic Part(f CL2=400kHz) 
Liquid Crystal Display Drive Part 
(fK=lkHz) 


ICC 






1.0 


mA 




- lee 






10.0 


pA 





Note: Applicable Terminal 

(1) CL1, CL2, DL1 , DL2, DR1 , DR2 , M , SHU, SHL2, FCS 

(2) DL1, DL2, DR1, DR2 



)f 



ht. 

ift 



HITACHI 45 




(3) Table of HD4A100 Pin Assignment 



Pin 
N o 


Power Supply 


Input 


Output 




Pin 

IN 


Power Supply 


Input 


Output 


i 






Y 

1 BO 




8 1 






v 

1 l . 


■ 

X 






Y 

1 11 




8 2 






v 

' 4 


8 






v 




3 8 






Y. 


4 






v 

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46 HITACHI